1. Field of the Invention
The present invention relates to memory devices based on phase change memory materials.
2. Description of Related Art
Phase change memory materials, like chalcogenide based materials and similar materials, can be caused to change phase between an amorphous state and a crystalline state by application of electrical current at levels suitable for implementation in integrated circuits. The generally amorphous state is characterized by higher electrical resistivity than the generally crystalline state, which can be readily sensed to indicate data. These properties have generated interest in using programmable resistive material to form nonvolatile memory circuits, which can be read and written with random access.
The change from the amorphous to the crystalline state, referred to as set herein, is generally a lower current operation. The change from crystalline to amorphous state, referred to as reset herein, is generally a higher current operation, which includes a short high current density pulse to melt or breakdown the crystalline structure, after which the phase change material cools quickly, quenching the phase change process and allowing at least a portion of the phase change material to stabilize in the amorphous state.
In phase change memory, data is stored by causing transitions in an active region of the phase change material between amorphous and crystalline states. The difference between the highest resistance R1 of the low resistance crystalline set state and the lowest resistance R2 of the high resistance amorphous reset state defines a read margin used to distinguish cells in the crystalline set state from those in the amorphous reset state. The data stored in a memory cell can be determined by determining whether the memory cell has a resistance corresponding to the low resistance state or to the high resistance state, for example by measuring whether the resistance of the memory cell is above or below a threshold resistance value within the read margin.
Materials within the GST-225 family include GeSbTe compositions along the Sb2Te3 and GeTe tie line as reported in “Structural, electric and kinetic parameters of ternary alloys of GeSbTe”, E. Morales-Sanchez, Thin Solid Films 471 (2005) 243-247. Relatively low crystallization temperature Tx of materials in the GST-225 family (e.g., Tx˜150° C.) can cause phase change memory cells fabricated from materials in the GST-225 family undergo undesired transformation from the amorphous reset state to the crystalline set state at elevated temperatures. The undesired transformation of the phase change material within the active region of memory cells at elevated operation temperatures leads to the creation of false data and the loss of desired stored data.
Many embedded system applications such as automotive electronics require pre-coding of memory devices where data are pre-programmed into a memory chip before the memory chip is mounted onto a substrate such as a printed circuit board (PCB). During the mounting process, the memory chip is subject to thermal cycles for solder reflow that can reach an elevated temperature of 260° C. The relatively low crystallization temperature of materials in the GST-225 family severely limits usability of memory devices based on materials in the GST-225 family in embedded system applications as data pre-coded in GST-225 based memory devices can be lost after the memory devices are mounted due to the elevated temperature of the mounting process.
It is therefore desirable to provide a phase change material with a high crystallization temperature to prevent undesired transformation from the amorphous reset state to the crystalline set state at elevated temperatures. It is also desirable to provide a method for programming a memory including memory cells based on the phase change material with a high crystallization temperature.